1. Technical Field
This disclosure generally relates to phase locked loops (PLLs), and more specifically relates to a PLL with multiple voltage controlled oscillators having different frequency ranges including a high frequency ring voltage controlled oscillator.
2. Background Art
A phase-locked loop or phase lock loop (PLL) is a control system that generates an output signal whose phase is related to the phase of an input signal. Phase-locked loops are widely employed in radio, telecommunications, computers and other electronic applications. PLLs often employ voltage controlled oscillators (VCOs) to generate a variable high frequency signal required by the PLL. One typical use of a PLL is in a high speed serializer/deserializer (HSS). Serializer/deserializer is often shortened to SerDes (pronounced sir-deez).
A SerDes is a pair of functional blocks commonly used in high speed communications to compensate for limited input/output. These blocks convert data between serial data and parallel interfaces in each direction. The primary use of a SerDes is to provide serial data transmission over a single/differential line in order to minimize the number of I/O pins and interconnects for the transmission of the data.